DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 21

• Manufacturer Part Number: DM9008AEP_06
• Description: Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.28 Early Transmit Control/Status Register ( 30H )
6.29 Check Sum Control Register ( 31H )
6.30 Receive Check Sum Status Register ( 32H )
6.31 LED Pin Control Register ( 34H )
Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
4~2
1~0
7~3
7:2
Bit
Bit
Bit
Bit
7
6
5
2
1
0
7
6
5
4
3
2
1
0
1
RESERVED
RESERVED
UDPCSE
Reserved
TCPCSE
RCSEN
IPCSE
Name
Name
Name
UDPS
UDPP
DCSE
Name
TCPS
TCPP
ETS2
ETS1
GPIO
ETE
ETT
IPS
IPP
HPS0, RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RO
HPS0,RO
PS0,RO
000,RO
Default
Default
Default
Default
P0,RW
0,RO
Early Transmit Enable
Enable bits[2:0]
Early Transmit Status II
Early Transmit Status I
Reserved
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
----- ----
0
0
1
1
Reserved
UDP CheckSum Generation Enable
TCP CheckSum Generation Enable
IP CheckSum Generation Enable
UDP CheckSum Status
1: checksum fail, if UDP packet
TCP CheckSum Status
1: checksum fail, if TCP packet
IP CheckSum Status
1: checksum fail, if IP packet
UDP Packet
TCP Packet
IP Packet
Receive CheckSum Checking Enable
When set, the checksum status (bit 7~2) will be stored in packet’s first byte(bit
7~2) of status header respectively.
Discard CheckSum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
Reserved
LED act as General Purpose signals in 16-bit mode
1: Pin 38/39 (LED2/1) act as the general purpose pins that are controlled by
registers 1Eh bit 2/1 and 1Fh bit 2/1 respectively.
0
1
0
1
: 12.5%
: 25%
: 50%
: 75%
threshold
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Ethernet Controller with General Processor Interface
Description
Description
Description
Description
DM9008AEP
21