DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 25
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DM9008AEP_06
Manufacturer Part Number
DM9008AEP_06
Description
Ethernet Controller with General Processor Interface
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet
1.DM9008AEP_06.pdf
(50 pages)
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6.44 Interrupt Status Register (FEH)
6.45 Interrupt Mask Register (FFH)
Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RESERVED
RESERVED
LNKCHGI
IOMODE
LNKCHG
UDRUNI
UDRUN
Name
Name
ROOI
ROO
PAR
ROI
PRI
RO
PTI
PR
PT
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
HPS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Default
Default
T0, RO
RO
RO
Link Status Change
Transmit Underrun
Receive Overflow
Enable Link Status Change Interrupt
Enable Transmit Underrun Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
0 :
1:
Reserved
Receive Overflow Counter Overflow
Packet Transmitted
Packet Received
Enable the SRAM read/write pointer to automatically return to the start
address when pointer addresses are over the SRAM size. Driver needs to
set. When driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Packet Received Interrupt
16-bit mode
8-bit mode
Ethernet Controller with General Processor Interface
Description
Description
DM9008AEP
25
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