DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 13

• Manufacturer Part Number: DM9008AEP_06
• Description: Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
P = power on reset default value
H = hardware reset default value
S = software reset default value
6.1 Network Control Register (00H)
Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
1
0
X
MRCMDX1
MWCMDX
2:1
MRCMDX
Bit
MWCMD
MRCMD
7
6
5
4
3
0
MWRH
TXPLH
MWRL
MRRH
TXPLL
MRRL
IMR
ISR
RESERVED
RESERVED
WAKEEN
Name
FCOL
Bit set to logic one
Bit set to logic zero
No default value
FDX
RST
LBK
Memory Data Pre-Fetch Read Command Without Address
Increment Register
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Register
Register
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Mask Register
Memory Data Write Command Without Address Increment
Memory Data Write Command With Address Increment
Interrupt Status Register
PHS0,RW
PHS0,RO
PH0,RW
PH0,RW
PHS00,
Default
P0,RW
0,RO
RW
Reserved
Wakeup Event Enable work in 8-bit mode
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
Reserved
Force Collision Mode, used for testing
Full-Duplex Mode of the internal PHY.
Loopback Mode
Bit
Software reset and auto clear after 10us
0
0
2 1
0
1
1
X
Normal
MAC Internal loopback
(Reserved)
Ethernet Controller with General Processor Interface
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
Description
F0H
F1H
F2H
F4H
F5H
F6H
F8H
FAH
FBH
FCH
FDH
FFH
FEH
DM9008AEP
00H
00H
00H
00H
XXH
XXH
00H
XXH
XXH
XXH
XXH
XXH
00H
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