BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 245
![no-image](/images/no-image-200.jpg)
BT8375
Manufacturer Part Number
BT8375
Description
single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.BT8375.pdf
(323 pages)
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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
RDELAY[5:0]
RSLIP_RD
RSLIP_WR
TDELAY[5:0]
TSLIP_WR
TSLIP_RD
N8370DSE
0DB—RSLIP Phase Status (RPHASE)
0DC—TSLIP Phase Status (TPHASE)
RDELAY[5]
TDELAY[5]
7
7
RDELAY[4]
TDELAY[4]
RSLIP Buffer Delay—The difference between the RX and RSB timebase in time slot intervals,
reported once per frame, coincident with RFRAME interrupt [ISR3; addr 008]. Actual delay
may vary significantly, depending on which time slots are assigned.
Active Receiver Slip Buffer Half—Indicates which half of the receive slip buffer is currently
receiving data from the receiver (0 = RSLIP_LO, 1 = RSLIP_HI). The processor can read data
from the opposite buffer half.
Active RSB Slip Buffer Half—Indicates which half of the receive slip buffer is currently
supplying data to the Receive System Bus (0 = RSLIP_LO, 1 = RSLIP_HI). The processor can
write data to the opposite buffer half.
TSLIP Buffer Delay—The difference between the TSB and TX timebase in time slot intervals,
reported once per frame, coincident with the TFRAME interrupt [ISR3; addr 008]. The actual
delay may vary significantly, depending on which time slots are assigned.
Active Transmitter Slip Buffer Half—Indicates which half of the transmit slip buffer is
currently supplying data to the transmitter (0 = TSLIP_LO, 1 = TSLIP_HI). The processor can
write data to the opposite buffer half.
Active TSB Slip Buffer Half—Indicates which half of the transmit slip buffer is currently
receiving data from the Transmit System Bus (0 = TSLIP_LO, 1 = TSLIP_HI). The processor
can read data from the opposite buffer half.
6
6
RDELAY[3]
TDELAY[3]
5
5
000000 = RX to RSB delay in the range of 0–7 bits
111111 = RX to RSB delay in the range of 504–511 bits
000000 = TSB to TX delay in the range of 0–7 bits
111111 = TSB to TX delay in the range of 496–503 bits
|
|
RDELAY[2]
TDELAY[2]
4
4
Conexant
RDELAY[1]
TDELAY[1]
3
3
RDELAY[0]
TDELAY[0]
2
2
RSLIP_WR
TSLIP_WR
3.17 System Bus Registers
1
1
RSLIP_RD
TSLIP_RD
0
0
3-127
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