BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 240

• Manufacturer Part Number: BT8375
• Description: single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.17 System Bus Registers
FRZ_OFF/FRZ_ON
THRU
3-122
NOTE(S):
D-bit update.
Signaling Bit
New Input
Signaling State During Current Multiframe
Non-Debounced signaling always transfers buffered ABCD input to buffered ABCD output coincident with the
0
1
1
0
1
0
0
1
Manual Signaling Update and SIGFRZ Output—Allows the processor to manually control
updates of the receive signaling buffer [RSIGn; addr 1A0–1BF], the signaling stack [addr
0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pin’s output
state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. The
receive ABCD input signaling is placed into the STACK and RSIG buffers according to the
modes shown below. Stack updates are individually enabled on a per-channel basis according
to SIG_STK [addr 180–19F].
Enable Transparent Robbed-Bit Signaling—RMSYNC is forced to align with respect to RX
timebase and follow each change of receiver's multiframe alignment, plus any frame offset
caused by RSLIP buffer delay. In this manner, RMSYNC is able to retain its signaling
multiframe alignment with respect to RPCMO output data frames. THRU mode is required
when RSLIP is configured in Bypass mode. It is also useful for ADPCM transcoder systems
that utilize robbed-bit signaling during frames other than normal (modulo 6) signaling frames,
and therefore cannot utilize RPCMO signaling reinsertion in ADPCM coded channels. During
THRU mode, RMSYNC must be programmed as an output [PIO; addr 018]. RMSYNC can
follow a change of RX multiframe alignment without generating an alarm indication (e.g.,
receiver change of SF alignment without accompanying loss of basic frame alignment).
FRZ_ON
Buffered Input
from Previous
Signaling Bit
(RSIGn[3:0])
X
X
0
0
0
1
Multiframe
0
0
1
1
1
1
0
0
FRZ_OFF
0
0
0
1
1
0
0 = no effect
1 = transparent robbed-bit signaling
Buffered Output
Signaling Bit
(RSIGn[7:4])
SIG_STK
0
0
0
0
1
1
1
1
X
X
0
1
0
1
Conexant
Interrupt
Updated from Input
Signaling State Updated at the End of Current Multiframe
Bit (RSIGn[3:0])
X
X
X
Signaling Bit is
0
1
0
Buffered Input
SIGFRZ
Signaling
Fully Integrated T1/E1 Framer and Line Interface
0
1
1
0
1
0
0
1
Pin
0
1
0
0
0
1
Buffered Output
ABCD Changes
ABCD Changes
(RSIGn[7:4])
Signaling Bit
No Update
No update
No update
No update
STACK
0
0
1
0
1
1
0
1
Bt8370/8375/8376
Change Output
Change Output
Debounce
Debounce
All ABCD
All ABCD
All ABCD
All ABCD
No Update
No update
Notes
N8370DSE
RSIGn