BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 231

• Manufacturer Part Number: BT8375
• Description: single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
EMBED
SBI[3:0]
N8370DSE
EMBED instructs the transmit framer (refer to [TABORT; addr 071] to align TX timebase with
respect to frame and multiframe alignment embedded in TXDATA, the transmit line rate data
output from TSLIP. If TSLIP is enabled, EMBED is inactive, and overhead is bypassed, TX
timebase is not guaranteed to align to TXDATA, and bypassed overhead cannot reliably pass
through TSLIP. EMBED is applicable to all system bus modes.
System Bus Interface mode—Defines transmit and receive system bus data format. System
buses operate in one of nine basic formats which differ in the number of total available data
time slots and the associated system bus clock rate. If the total time slots are a multiple of 32,
SBI also defines which bus group of 32 byte-interleaved time slots are assigned to the
respective device.
NOTE(S):
addr 072] is in Bypass or Transparent mode.
TS0 Embedded The offline framer examines TXDATA to align TX timebase to
G.802
Embedded
EMBED
SBI[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
0
1
1
Embedded F-bits reach TX output only if frame formatter [TFRM;
the embedded FAS pattern. If MFAS is also enabled
[TFRAME; addr 070], the transmit online framer examines
TXDATA to align TX timebase to the embedded MFAS pattern.
While EMBED is active, TXDATA output is monitored, and
transmit frame errors are reported in ISR0 [addr 00B].
Embedded TS0 supports E1 overhead bypass options for
applications where TSLIP buffer is enabled.
Automatically supports ITU–T Recommendation G.802, which
defines frame format conversion between T1 and E1 line rates
by locating T1 F-bits in Bit 1 of time slot 26 of each system bus
frame. G.802 embedded mode is applicable for system buses
that are 1x, 2x, or 4x multiples of the E1 line rate. Full
implementation of G.802 also requires the processor to program
TS0, TS16, and TS26–TS31 as unassigned system bus time
slots [SBCn; addr 0E0–0FF].
T1/E1N
Conexant
x
0
1
Mode
128A
128B
128C
128D
64A
64B
32
24
24
Clock (Kobe)
Transmit framer searches TPCMI
TS0 Embedded; search TXDATA
8192
8192
8192
8192
4096
4096
2048
1544
1536
Embedded Framing Mode
G.802; search TXDATA
Total Time Slots
24 + F-bit
128
128
128
128
64
64
32
24
3.17 System Bus Registers
Bus Group
Group 0
Group 1
Group 2
Group 3
Group 0
Group 1
—
—
—
3-113