K4H281638L-LCB3 SAMSUNG [Samsung semiconductor], K4H281638L-LCB3 Datasheet - Page 10

• Manufacturer Part Number: K4H281638L-LCB3
• Description: 128Mb L-die DDR SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation. No power sequencing is specified during power up and power down given the following
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At least one of these two conditions must be met.
Except for CKE, inputs are not recognized as valid until after V
level after V
outputs will be in the High–Z state, where they will remain until driven in normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 µs delay prior to applying an executable com-
mand. Once the 200 µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought
HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command
should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the
Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A PRECHARGE ALL command should be applied, placing the device in the ”all banks idle” state.
Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Reg-
ister, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be performed. Following
these cycles, the DDR SDRAM is ready for normal operation.
7.0 FUNCTIONAL DESCRIPTION
7.1 Power-up & Initialization Sequence
K4H281638L
V
V
V
V
V
V
V
DD
TT
REF
DDQ
DDQ
TT
REF
is limited to 1.35 V, AND
is driven after or with V
and V
tracks V
is driven after or with V
is driven after or with V
< V
DD
DD
is applied. Maintaining an LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS
DDQ
+ 0.3 V AND
DDQ
are driven from a single power converter output, AND
/2 OR, the following relationships must be followed:
DDQ
DDQ
DD
such that V
such that
such that V
TT
REF
< V
< V
DDQ
DDQ
+ 0.3 V, AND
+ 0.3 V.
REF
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is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
Rev. 1.2 Feburary 2009
DDR SDRAM