USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 44

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

6.2.2.3
This is detected by the SIE when the idle condition on the USB bus occurs for a duration of more than 3ms. Upon
detection of this condition via the SUSPEND bit of ISR_1, the 8051 will place the USB97C201 into a low power mode
via the USB_SUSPEND bit and enter into a power down state.
6.2.2.4
When a SETUP token is recognized, the following sequence happens.
1.
2.
3.
4.
5.
6.2.2.5
This global resume condition is recognized asynchronously and does not require the SIE clock running. Upon
recognition it causes the following. A USB RESET will be interpreted as a RESUME if it occurs while clocks are
stopped.
If the USB_RESUME and USB_STAT bits are unmasked, then a ISR_0 interrupt (USB_STAT) is generated to the
8051. Also the RESUME bit in the WU_SRC1 register will be set and can generate an interrupt, if unmasked.
The SIE_SUSPEND bit is cleared automatically and the SIE resumes from power down state.
6.2.2.6
When the 8051 is required to go into power down state, the SIE_SUSPEND should be set. When a remote wakeup
event is desired, the 8051 is responsible to clear the SIE_SUSPEND, and set the SIE_RESUME bits.
6.2.3
The SIE also handles autonomously several standard device requests received on Endpoint 0.
These requests are:
These events (except SET_ADDRESS, GET_INTERFACE (always returns 0), and GET_CONFIGURATION) are
indicated in the SIE_STATUS register, which can generate an interrupt to the 8051 core’s INT3 line. The
configuration number, resulting from the SET_CONFIGURATION command is stored in the USB_CONF register.
This value is used when reporting to the host on a GET_CONFIGURATION Command, also. All other device
requests are handled normally and will generate the SETUP status bit when received.
6.2.4
Upon POR or the detection of USB RESET, the Configuration of the device is set to “0”. The host may change its
Configuration state to “1” with a “SET CONFIGURATION” command on Endpoint 0. All other Configuration number
requests by the host will result in a STALL condition on Endpoint 0. For Configuration 0, only Endpoint 0 RX and TX
are enabled, while all endpoints are enabled for Configuration 1.
6.3 IDE Controller Description
This is an ATA-66 core. The PIO I/O address range for the ATA interface in the 8051 XDATA space is decoded in
the range of 0X31F0 to 0X31F7, and 0x33F6
Transfers to/from SRAM will occur from/to the 16 bit ATA Data Port at CS0=1, CS1=0, A2-A0= 0.
SMSC DS – USB97C201
Independent of the state of SETUP bit, the setup data packet is received on EP0RX and ACK is sent for the
received setup packet.
The stall condition, if any, for EP0TX and EP0RX are cleared, as well as the EP0RX_BC and EP0TX_BC
registers and the TX bit of EP0_CTL register .
The internal DTOG bit for both EP0TX and EP0RX are set to one.
The EP0RX_BC register is cleared, allowing the subsequent data packet( if not zero length) to be written into
the start of the buffer.
The SETUP bit in ISR_0 register is set. Until the SETUP bit is cleared by the 8051, all OUT packets to EP0RX
are NACKed.
SET_CONFIGURATION
GET_CONFIGURATION
SET_FEATURE_ENDPOINT_HALT
CLEAR_FEATURE_ENDPOINT_HALT
SET_FEATURE_REMOTE_WAKE_UP
CLEAR_FEATURE_REMOTE_WAKE_UP
GET_INTERFACE
SET_INTERFACE
SET_ADDRESS
STANDARD DEVICE REQUESTS
SIE CONFIGURATIONS
Suspend
Setup token Arrival
Resume
Remote Wakeup
PRELIMINARY
Page 44
Rev. 03/25/2002