USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 21

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Note 1: The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an
SMSC DS – USB97C201
interrupt.
[7:0]
[7:0]
BIT
BIT
BIT
7
6
5
4
3
2
1
0
(0x96- RESET=0x12)
(0x95- RESET=0xXX)
(0x94- RESET=0xFF)
Resereved
SUSPEND
ZLP_EP0
ATA_PIO
EP1RX
EP0RX
EP1TX
EP0TX
NAME
DEV_REV
DEV_ID
XXh
12h
IMR_1
Table 11 - Device Identification Register
Table 10 - Device Revision Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
PRELIMINARY
Table 9 - Interrupt 1 Mask
This register defines additional revision information
used internally by SMSC
Reserved. This bit should never be written to a “0”.
0 = Enable Interrupt
1 = Mask Interrupt
ATA PIO Complete Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 1 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 1 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 0 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 0 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SUSPEND Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
This register defines additional revision information
used internally by SMSC. The value is silicon revision
dependent.
Zero Length Packet Interrupt Mask
Page 21
DEVICE IDENTIFICATION REGISTER
INTERRUPT 1 MASK REGISTER
DEVICE REVISION REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002