USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 19

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

6.1.4
6.1.4.1
The bits in this register (except bit 7) are set to their POR values by writing a ‘1’ to the corresponding bit. If not
masked by the corresponding bit in the IMR0 mask register, a “1” on any of these bits will generate a “1” on the 8051
core’s external INT0 input.
SMSC DS – USB97C201
MCU REGISTER DESCRIPTIONS
MCU Runtime Registers
BIT
7
6
5
4
3
2
1
0
(0x80 - RESET=0x0C)
USB_STAT
RAMWR_B
RAMWR_A
RAMRD_B
RAMRD_A
ISR_0
Reserved
ATA_IRQ
SETUP
NAME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 6 - Interrupt 0 Source Register
R
R
PRELIMINARY
1= USB Bus System Event has occurred. Check USB_STAT
register for the specific event(s). This must be cleared by
clearing the USB_STAT register.
1= A SETUP packet was received on Endpoint 0. The EP0RX
bit of ISR_1 will not be set. If another SETUP packet is
received on Endpoint 0 while this bit is high, the bit will go low
and then immediately high again, to signal the duplicate
SETUP. If all other bits in this register are clear and the INT0
of the 8051is configured for edge triggering, then another
interrupt will be generated within the 8051. The firmware must
clear this bit by writing a "1" to it to allow the Enpoint 0 buffer
to receive subsequent data packets during the SETUP
transaction. Receipt of these packets will set EP0RX in ISR_1.
This bit always reads a “0”.
External interrupt input from the ATA-66 Interface.
1 = An ATA interrupt has occurred.
1 = The current transfer from the SRAM B Buffer has been
completed. See Sections 6.7 and 6.9 for more detail. This bit
is also cleared by writing a “1” to the RAMRD_TOGGLE bit of
the EP2_CTL register.
1 = The current transfer from the SRAM A Buffer has been
completed. See Sections 6.7 and 6.9 for more detail. . This bit
is also cleared by writing a “0” to the RAMRD_TOGGLE bit of
the EP2_CTL register.
1 = The current transfer to the SRAM B Buffer has been
completed. This bit may be cleared by the internal hardware
state machine while operating in “Auto Transfer” mode. See
Sections 6.7 and 6.9 for more detail.
1 = The current transfer to the SRAM A Buffer has been
completed. This bit may be cleared by the internal hardware
state machine while operating in “Auto Transfer” mode. See
Sections 6.7 and 6.9 for more detail.
Page 19
INTERRUPT 0 SOURCE REGISTER
DESCRIPTION
Rev. 03/25/2002