USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 37

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Notes:
SMSC DS – USB97C201
Any bit that is high in this register, if not masked by the corresponding mask bit in the NAK_MSK register will
generate INT5 to the 8051.
A bit in this register may be cleared by writing a “1” to it.
BIT
BIT
BIT
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(0xDA - RESET=0x00)
(0xD7 - RESET=0x00)
(0xD9- RESET=0xFF)
NAK2RX
NAK1RX
NAK0RX
NAK1TX
NAK0TX
NYET2RX
NYET0RX
Reserved
Reserved
Reserved
NAK2RX
NAK1RX
NAK0RX
NAK2TX
NAK1TX
NAK0TX
NAME
RXERR
TOKEN
STALL
NAME
NAME
DTOG
NAK_MSK
USB_ERR
CRC
NAK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/w
R
R
R
R
R
R
R
R
Table 49 – NAK Mask Register
Table 50 – USB Error Register
PRELIMINARY
1 = indicates that an NAK has been sent to the host on
Endpoint 2 in response to an OUT token.
1 = indicates that an NAK has been sent to the host on
Endpoint 1 in response to an IN token.
1 = indicates that an NAK has been sent to the host on
Endpoint 1 in response to an OUT token.
1 = indicates that an NAK has been sent to the host on
Endpoint 0 in response to an IN token.
1 = indicates that an NAK has been sent to the host on
Endpoint 0 in response to an OUT token.
1 = Prevents generation of the 8051 INT5 interrupt when the
NYET2RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NYET0RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK2TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK2RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK1TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK1RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK0TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK0RX bit is set in the NAK register.
This bit always reads a “0”.
When set, this bit indicates that an unexpected token has
been received on one of the device’s endpoints.
This bit always reads a “0”.
When set, indicates that a token has been received on a
endpoint of the device while that endpoint is in the STALL
condition.
When set, indicates that a data packet has been received
on one of the device’s endpoints that has an incorrect data
toggle.
When set, indicates that a packet has been received on one
of the device’s endpoint with an error in FS mode.
This bit always reads a “0”.
When set, indicates that a packet with an incorrect CRC
Page 37
USB ERROR REGISTER
NAK MASK REGISTER
NAK REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002