USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 20

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Note1: The mask bits do not prevent the status in the ISR_0 register from being set, only from generating an
interrupt.
Note 1: The bits (except for bit 5)in this register are cleared by writing a ‘1’ to the corresponding bit. If not masked by
the corresponding bit in the IMR1 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s
external INT1 input.
SMSC DS – USB97C201
BIT
7
6
5
4
3
2
1
0
(0x90- RESET=0x00)
BIT
7
6
5
4
3
2
1
0
SUSPEND
(0x93- RESET=0xFF)
ZLP_EP0
Reserved
ATA_PIO
EP1RX
EP0RX
EP1TX
EP0TX
NAME
ISR_1
USB_STAT
RAMWR_B
RAMWR_A
RAMRD_B
RAMRD_A
IMR_0
Reserved
ATA_IRQ
SETUP
NAME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 8 - Interrupt 1 Source Register
PRELIMINARY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1= A ZLP has been received on EP0RX.
This bit always reads a “0”.
This bit reflects that state of the PIO_COMPLETE bit (bit 6) of
the ATA_CTL register. It cannot be written directly.
1 = A Packet was successfully received on Endpoint 1 and
stored in the Buffer SRAM. OUT tokens will be NAK’d until this
bit is cleared.
1 = A Packet was successfully transmitted on Endpoint 1 from
the Buffer SRAM. IN tokens will be NAK’d until this bit is
cleared.
1 = A non-SETUP, non ZLP Packet (see ISR_0 SETUP bit)
was successfully received on Endpoint 0 and stored in the
Buffer SRAM. OUT tokens will be NAK’d until this bit is
cleared.
1 = A Packet was successfully transmitted on Endpoint 0 from
the Buffer SRAM. IN tokens will be NAK’d until this bit is
cleared.
Suspend – If 3ms of IDLE state are detected by the hardware,
then this bit will be set.
Table 7 - Interrupt 0 Mask
USB Bus System Event interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
SETUP interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
Reserved.
External ATA-66 interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer B Output Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer A Output Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer B Input Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer A Input Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Page 20
INTERRUPT 1 SOURCE REGISTER
INTERRUPT 0 MASK REGISTER
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002