USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 30

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

The bits in this register (except bit 2) are cleared by writing a ‘1’ to the corresponding bit. These bits are ORed, if
unMASKED in the USB_MSK register, and drive a latch for the USB_STAT bit in the ISR_0 register.
Note1: The mask bits do not prevent the status in the USB_STAT register from being set, only from setting the
SMSC DS – USB97C201
BIT
BIT
[7]
[7]
6
5
4
3
2
1
0
USB_STAT bit in the ISR_0 register.
6
5
4
3
2
1
0
(0xAC - RESET=0xFF)
(0xAB - RESET=0x00)
USB_RESUME
USB_RESUME
USB_RESET
USB_RESET
EP2_ERR
EP2_ERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ERROR
ERROR
NAME
NAME
USB_STAT
USB_MSK
2.0
2.0
Table 27 – USB Bus Status Mask Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 26 - USB Bus Status Register
R
R
R
R
R
R
R
PRELIMINARY
This bit always reads “0”.
by the DIR bit of EP2_CTL register was received, ie an
unexpected IN or OUT token.
1 = Host is high speed capable. This bit is set if high speed
signaling is received from the host.
This is only valid if the USB97C201 is in the SUSPEND
state via bit 0 of the SIE_CONF register.
1 = Indicates that a USB Error has been detected. See the
USB_ERR register for details. This bit is cleared by clearing
the USB_ERR register.
This bit always reads “0”.
This bit always reads “0”.
1 = Indicates that a token in the opposite direction inferred
1 = Indicates that RESUME signaling has been detected.
1 = Indicates that a USB Reset has been detected.
This bit always reads “1”.
This bit always reads “1”.
This bit always reads “1”.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the EP2_ERR bit is set in the USB_STAT
register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the 2.0 bit is set in the USB_STAT register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESUME bit is set in the
USB_STAT register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESET bit is set in the USB_STAT
register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the ERROR bit is set in the USB_STAT
register.
Page 30
USB BUS STATUS MASK REGISTER
USB BUS STATUS REGISTER
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002