USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 28

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Note 1: The bits 1 and 2 in this register are cleared by writing a ‘1’ to the corresponding bit.
Note 2: Unmasked Wakeup Source bits restart the 8051 when its clock is stopped. This restarts the Ring Oscillator
Note 3: To initiate USB Remote Wakeup, the SIE_Resume bit should be used in the SIE_CONF register.
Note 1: Interrupt events enabled by these bits are Ored and routed to the INT2 external interrupt input of the 8051
SMSC DS – USB97C201
[7:3]
BIT
2
1
0
and crystal oscillator for the MCU to resume from <500µA operation.
core.
[7:3]
(0XA0 – RESET=0x00)
BIT
2
1
0
(0XA6 - RESET=0xFF)
USB_Reset
WU_MSK_1 (Note 1)
Reserved
WU_SRC_1
EXT_INT
Resume
NAME
USB_Reset
Reserved
EXT_INT
Resume
NAME
R/W
R/W
R/W
R/W
R
Table 22 - Wakeup Source 1 Register (INT2)
R/W
R/W
R/W
R/W
R
Table 23 - Wakeup Mask 1 Register
Reserved
This bit is set when the SIE detects simultaneous logic lows on D+
and D- (Single-Ended 0) for 32 to 64 full speed bit times, or 4 to 8
low speed bit times (or 2.5<t<5.5us). The USB_Reset signal may be
as long as 10ms. SETUP tokens can be NAK'd for up to 10ms after
the Reset signal is released.
This bit is set on detection of Global Resume state (when there is a
transition from the "J" state while in Global Suspend).
This bit will be set if the ATA_IRQ bit of the ISR_0 register is set OR
if the 8051 INT4 signal (GPIO Interrupts) is high.
PRELIMINARY
External wakeup event.
0 = Enabled
1 = Masked
External wakeup event.
0 = Enabled
1 = Masked
External wakeup event.
0 = Enabled
1 = Masked
This bit always reads “1”.
Page 28
WAKEUP SOURCE 1
WAKEUP MASK 1
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002