MT9LSDT1672G-10E MICRON [Micron Technology], MT9LSDT1672G-10E Datasheet - Page 9

• Manufacturer Part Number: MT9LSDT1672G-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

Commands
commands. This is followed by a written description of
each command. For a more detailed description of
TRUTH TABLE 1 – COMMANDS AND DQMB OPERATION
(Note: 1)
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Truth Table 1 provides a quick reference of available
2. A0-A11 define the op-code written to the Mode Register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8/A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
5. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0, BA1 are
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
“Don’t Care.”
9
CS# RAS# CAS# WE# DQMB
H
L
L
L
L
L
L
L
–
–
L
commands and operations refer to the 64Mb, 128Mb
x4, x8, x16 SDRAM datasheets.
X
H
H
H
H
L
L
L
L
–
–
REGISTERED SDRAM DIMMs
H
H
X
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
X
H
H
H
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
H
X
L
8
8
8, 16 MEG x 72
Bank/Row
Bank/Col
Bank/Col Valid
Op-Code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
©1999, Micron Technology, Inc.
Active
DQs NOTES
ADVANCE
X
X
X
X
X
X
X
6, 7
3
4
4
5
2
8
8