MT9LSDT1672G-10E MICRON [Micron Technology], MT9LSDT1672G-10E Datasheet

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MT9LSDT1672G-10E

Manufacturer Part Number
MT9LSDT1672G-10E
Description
SYNCHRONOUS DRAM MODULE
Manufacturer
MICRON [Micron Technology]
Datasheet
SYNCHRONOUS
DRAM MODULE
FEATURES
• JEDEC-standard 168-pin, dual in-line memory
• PC133- and PC100-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce
• Utilizes 133 MHz and 125 MHz SDRAM compo-
• ECC-optimized pinout
• 64MB (8 Meg x 72) and 128MB (16 Meg x 72)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on
• Internal pipelined operation; column address can
• Internal SDRAM banks for hiding row access/
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
OPTIONS
• Package
• Frequency/CAS Latency*
*Device latency only; extra clock cycle required due to input register.
KEY SDRAM COMPONENT
TIMING PARAMETERS
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
MARKING
MODULE
module (DIMM)
loading
nents
positive edge of PLL clock
be changed every clock cycle
precharge
168-pin DIMM (gold)
133 MHz/CL = 2
(7.5ns, 133 MHz SDRAMs)
133 MHz/CL = 3
(7.5ns, 133 MHz SDRAMs)
100 MHz/CL = 2
(8ns, 125 MHz SDRAM)
-13E
-133
-10E
GRADE
SPEED
-7E
-75
-8E
LATENCY
CAS
2
3
2
ACCESS
TIME
5.4ns
5.4ns
6ns
SETUP
TIME
1.5ns
1.5ns
2ns
MARKING
-13E
-133
-10E
G
HOLD
TIME
0.8ns
0.8ns
1ns
1
MT9LSDT872, MT9LSDT1672
For the latest data sheet, please refer to the Micron Web
site:
NOTE: Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
PIN SYMBOL PIN SYMBOL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1
2
3
4
5
6
7
8
9
www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT (FRONT VIEW)
DQMB0
DQMB1
REGISTERED SDRAM DIMMs
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WE#
DNU
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
V
V
V
A10
BA1
V
V
CK0
CB0
CB1
S0#
V
V
V
V
NC
NC
A0
A2
A4
A6
A8
DD
DD
DD
DD
DD
SS
SS
SS
SS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
63
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
168-PIN DIMM
RFU (CKE1)
DQMB2
DQMB3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DNU
DNU
V
V
V
CK2
SDA
V
S2#
CB2
CB3
SCL
V
V
V
V
V
WP
NC
NC
NC
NC
NC
DD
DD
DD
DD
SS
SS
SS
SS
SS
PIN SYMBOL PIN SYMBOL
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
8, 16 MEG x 72
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
RFU (A12)
RFU (S1#)
DQMB4
DQMB5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CAS#
RAS#
V
V
CB4
CB5
V
BA0
A11
V
CK1
V
V
V
V
NC
NC
A1
A3
A5
A7
A9
DD
DD
DD
DD
SS
SS
SS
SS
©1999, Micron Technology, Inc.
ADVANCE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
RFU (A13)
RFU (S3#)
DQMB6
DQMB7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CKE0
REGE
V
V
V
CK3
SA0
SA1
SA2
V
CB6
CB7
V
V
V
V
V
NC
NC
NC
NC
NC
DD
DD
DD
DD
SS
SS
SS
SS
SS

Related parts for MT9LSDT1672G-10E

MT9LSDT1672G-10E Summary of contents

Page 1

... TIME 41 V 1.5ns 0.8ns 42 CK0 1.5ns 0.8ns NOTE: Symbols in parentheses are not used on these modules but may be used 2ns 1ns for other modules in this product family. They are for reference only. 1 ADVANCE 8, 16 MEG x 72 168-PIN DIMM PIN SYMBOL PIN SYMBOL ...

Page 2

... Meg x 72 MT9LSDT872G-10E__ 8 Meg x 72 MT9LSDT1672G-13E__ 16 Meg x 72 MT9LSDT1672G-133__ 16 Meg x 72 MT9LSDT1672G-10E__ 16 Meg x 72 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9LSDT1672G-133B1 GENERAL DESCRIPTION The MT9LSDT872 and MT9LSDT1672 are high-speed CMOS, dynamic random-access, 64MB and 128MB memories organized in a x72 configuration ...

Page 3

SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ures 1 and 2). SPD START CONDITION All ...

Page 4

MT9LSDT872 (64MB) AND MT9LSDT1672 (128MB) RAS# CAS# CKE0 WE# A0-A11 BA0 BA1 S0#, S2# DQMB0-DQMB7 PLL CLK 10K REGE NOTE: 1. All resistor values are 10 ohms unless otherwise specified Meg x 72 PC133/PC100 Registered ...

Page 5

... LOAD MODE REGISTER command. Input Write Protect: Serial presence-detect hardware write protect. Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input Register Enable ...

Page 6

... Reserved for Future Use: These pins are not connected on this module but are assigned pins on other SDRAM versions. – Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version MEG x 72 REGISTERED SDRAM DIMMs DESCRIPTION Micron Technology, Inc ...

Page 7

... TOTAL NUMBER OF SPD MEMORY BYTES 2 MEMORY TYPE 3 NUMBER OF ROW ADDRESSES 4 NUMBER OF COLUMN ADDRESSES 5 NUMBER OF BANKS 6 MODULE DATA WIDTH 7 MODULE DATA WIDTH (continued) 8 MODULE VOLTAGE INTERFACE LEVELS t 9 SDRAM CYCLE TIME, CK (CAS LATENCY = SDRAM ACCESS FROM CLOCK, (CAS LATENCY = 3) 11 MODULE CONFIGURATION TYPE ...

Page 8

... RESERVED 62 SPD REVISION 63 CHECKSUM FOR BYTES 0-62 64 MANUFACTURER’S JEDEC ID CODE 65-71 MANUFACTURER’S JEDEC ID CODE (CONT.) 72 MANUFACTURING LOCATION 73-90 MODULE PART NUMBER (ASCII) 91 PCB IDENTIFICATION CODE 92 IDENTIFICATION CODE (CONT.) 93 YEAR OF MANUFACTURE IN BCD 94 WEEK OF MANUFACTURE IN BCD 95-98 MODULE SERIAL NUMBER 99-125 MANUFACTURER-SPECIFIC DATA (RSVD) 126 ...

Page 9

... Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 REGISTERED SDRAM DIMMs commands and operations refer to the 64Mb, 128Mb x4, x8, x16 SDRAM datasheets. CS# RAS# CAS# WE# DQMB ...

Page 10

A11 A10 Unused Reserved Mode CAS Latency BT *Should program M11, M10 = “0, 0” to ensure compatibility with future devices. ...

Page 11

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply Relative Voltage on Inputs I/O Pins Relative to V ...................................... -1V to +4.6V SS Operating Temperature, T (ambient) ... 0°C to +70°C A Storage Temperature (plastic) .......... -55°C ...

Page 12

I SPECIFICATIONS AND CONDITIONS DD (Notes: 1- +3.3V ±0.3V) DD PARAMETER/CONDITION OPERATING CURRENT: Active Mode Burst = 2; READ or WRITE (MIN); CAS latency = 3 STANDBY CURRENT: Power-Down Mode; CKE = LOW; ...

Page 13

... AUTO REFRESH PERIOD PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command *Specifications for the SDRAM components used on the module Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 = +3.3V MHz. DD -13E ...

Page 14

NOTE: 1. This parameter is sampled The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T ≤ +70°C) is ensured initial pause of ...

Page 15

AC FUNCTIONAL CHARACTERISTICS (Notes: 1-7) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM ...

Page 16

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note +3.3V ±0.3V) DD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA OUT INPUT LEAKAGE CURRENT: ...

Page 17

SCL t SU:STA SDA IN SDA OUT SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL BUF HD:DAT t HD:STA 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 SPD EEPROM ...

Page 18

R (2X) .118 (3.00) (2X) .118 (3.00) .250 (6.35) PIN 1 .118 (3.00) PIN 168 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: ...

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