IDT72V8980PV IDT, Integrated Device Technology Inc, IDT72V8980PV Datasheet - Page 5

• Manufacturer Part Number: IDT72V8980PV
• Description: IC DGTL SW 256X256 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V8980PV

• Circuit: 1 x 8:8
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Other names: 72V8980PV

If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s
output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on
CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the
CCO output is transmitted in LOW. The contents of the 256 CCO bits of the CMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TX streams. For example, the contents of CCO bit in position 0 (corresponding
to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.
INITIALIZATION OF THE IDT72V8980
can be in any state. This is a potentially hazardous condition when multiple TX
TABLE 1 — INPUT STREAM TO OUTPUT
STREAM COMBINATIONS THAT CAN
PROVIDE THE MINIMUM 2-CHANNEL
DELAY
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
The contents of bit 1 (CCO) of each Connection Memory High Location (see
On initialization or power up, the contents of the Connection Memory High
Input
0
1
2
3
4
5
6
7
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
100000
Control Register
Output Stream
Connection Memory High
1,2,3,4,5,6,7
1,2,3,4,5,6,7
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
100001
3,4,5,6,7
3,4,5,6,7
5,6,7
5,6,7
Connection Memory Low
7
7
Data Memory
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
100010
CR
b
7
Figure 3. Address Mapping

CR
b
CR
6 CR
0
1
1
b
4 CR
b
5 CR
1
0
1
b
5
3
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
RESET
the TX serial streams will be put into high-impedance and the state of internal
registers and counters will be reset. As the connection memory can be in any
state after a power up, the ODE pin should be used to hold the TX streams in
high-impedance until the per-channel output enable control in the connection
memory high is appropriately programmed. The main difference between ODE
and reset is, reset alters the state of the registers and counters where as ODE
controls only the high-impedance state of the TX streams. RESET input is only
provided on the SSOP package.
TABLE 2 — ADDRESS MAPPING
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
b
A5 A4 A3 A2 A1 A0
4 CR
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
0
1
1
1
111111
•
•
•
During the microprocessor initialization routine, the microprocessor should
The reset pin is designed to be used with board reset circuitry. During reset
b
X
0
0
1
•
•
•
3 CR
X
0
0
1
•
•
•
b
2 CR
External Address Bits
X
0
0
1
•
•
•
b
1 CR
CR
X
0
0
1
•
•
•
0
0
0
0
1
1
1
1
b
2 CR
b
0
X
0
1
1
•
•
•
0
0
1
1
0
0
1
1
b
1 CR
HEX ADDRESS
Commercial Temperature Range
A5-A0
0
1
0
1
0
1
0
1
b
0
00-1F
20
21
3F
Stream
5705 drw07
•
•
•
0
1
2
3
4
5
6
7
Control Register
Channel 31
Channel 0
Channel 1
LOCATION
•
•
•
(2)
(2)
(2)
(1)