IDT72V8980PV IDT, Integrated Device Technology Inc, IDT72V8980PV Datasheet - Page 4

• Manufacturer Part Number: IDT72V8980PV
• Description: IC DGTL SW 256X256 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V8980PV

• Circuit: 1 x 8:8
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Other names: 72V8980PV

FUNCTIONAL DESCRIPTION (Cont'd)
Memory or Connection Memory. The Connection Memory is 16 bits wide and
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particular channel in the output stream so as to provide a one-to-one correspon-
dence between the two memories. This correspondence allows for per channel
control for each TX output stream. In Processor Mode, data output on the TX
stream is taken from the Connect Memory Low and originates from the
microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is
read from Data Memory using the address in Connection Memory. Data
destined for a particular channel on the serial output stream is read during the
previous channel time slot to allow time for memory access and internal parallel-
to-serial conversion.
CONNECTION MODE
are stored in the Connect Memory Low. The Connect Memory Low locations
are mapped to corresponding 8-bit x 32-channel output. The contents of the
Data Memory at the selected address are then transferred to the parallel-to-
serial converters. By having the output channel to specify the input channel
through the connect memory, input channels can be broadcast to several output
channels.
PROCESSOR MODE
locations which are to be output on the TX streams. The contents of the Connect
Memory Low are transferred to the parallel-to-serial converter one channel
before it is to be output and are transmitted each frame to the output until it is
changed by the CPU.
CONTROL
available in the IDT72V8980. Output channels are selected into specific modes
such as: Processor Mode or Connection mode and Output Drivers Enabled
or in three-state condition. There is also one bit to control the state of the CCO
output pin.
OUTPUT DRIVE ENABLE (ODE)
all TDM outputs will be placed in high impedance regardless Connect Memory
High programming. However, if ODE is HIGH, the contents of Connect Memory
High control the output state on a per-channel basis.
DELAY THROUGH THE IDT72V8980
streams results in a delay through the device. The delay through the IDT72V8980
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
RX
Data to be output on the serial streams may come from two sources: Data
In Connection Mode, the addresses of input source for all output channels
In Processor Mode the CPU writes data to specific Connect Memory Low
The Connect Memory High bits (Table 4) control the per-channel functions
The ODE pin is the master output control pin. If the ODE input is held LOW
The transfer of information from the input serial streams to the output serial
Serial Data
Receive
Streams
Figure 1. Connection Mode
Connection
Memory
Memory
Data
Serial Data
Transmit
Streams
5705 drw05
TX
4
device varies according to the combination of input and output streams and the
movement within the stream from channel to channel. Data received on an input
stream must first be stored in Data Memory before it is sent out.
serial-to-parallel converter. Likewise, before data leaves the device, it must
pass through the internal parallel-to-serial converter. This data preparation has
an effect on the channel positioning in the frame immediately following the
incoming frame—mainly, data cannot leave in the same time slot, on in the time
slot immediately following. Therefore, information that is to be output in the same
channel position as the information is input, relative to the frame pulse, will be
output in the following frame. As well, information switched to the channel
immediately following the input channel will not be output in the time slot
immediately following but in the next timeslot allocated to the output channel, one
frame later.
information entered the IDT72V8980 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This
situation is caused by the order in which input stream information is placed into
Data Memory and the order in which stream information is queued for output.
Table 1 shows the allowable input/output stream combinations for the minimum
2 channel delay.
SOFTWARE CONTROL
Register is addressed. If A5 input line is high, then the remaining address input
lines are used to select the 32 possible channels per input or output stream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8980 Data and
Connection memories. The IDT72V8980 memory mapping is illustrated in
Table 2 and Figure 3.
Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit
7 of the Control register) reads are from the Data Memory and writes are to the
Connect Memory as specified by the Memory Select Bits (Bits 4 and 3 of the
Control Register). The Memory Select bits allow the Connect Memory High or
LOW or the Data Memory to be chosen, and the Stream Address bits define
internal memory subsections corresponding to input or output streams.
output stream in Processor Mode; i.e., the contents of the Connect Memory LOW
(CML, see Table 5) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8980
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connect
Memory High (CMH) locations were set to HIGH, regardless of the actual value.
If PE is LOW, then bit 2 and 0 of each Connect Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
is to be switched to an output.
As information enters the IDT72V8980 it must first pass through an internal
Whether information can be output during a following timeslot after the
If the A5 address line input is LOW then the IDT72V8980 Internal Control
The data in the control register consists of Memory Select and Stream
The Processor Enable bit (bit 6) places EVERY output channel on every
Serial Data
Receive
Streams
Figure 2. Processor Mode
Microprocessor
Connection
Memory
Memory
Data
Commercial Temperature Range
Serial Data
Transmit
Streams
5705 drw06
TX