S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 84

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

24.5 128M pSRAM
25 AC Operating Conditions
25.1
82
Test Conditions (Test Load and Test Input/Output Reference)
Note: Standby mode is supposed to be set up after at least one active operation after power up. I
from the time when standby mode is set up.
Note: Including scope and jig capacitance.
Average Operating
Current
Input pulse level: 0.4 V to 2.2 V (16Mb, 32Mb, 128Mb); 0.3 V to 2.2 V
(64Mb)
Input rising and falling time: 5ns (16Mb, 32Mb); 3ns (64Mb, 128Mb)
Input and output reference voltage: 1.5V (16Mb, 32Mb); 0.5 x V
128Mb)
Output load (See Figure 25.1): 50pF (16Mb, 32Mb); 30pF (64Mb, 128Mb)
Item
Symbol
I
I
CC1
CC2
Cycle time=1µs, 100% duty, I
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V
Cycle time=t
CS1#=V
UB#=V
Other inputs=0-V
1. CS1# ≥ V
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
CC
IL
-0.2V, V
IL
, V
pSRAM Type 2
, CS2=V
Figure 25.1 Output Load
IN
Dout
CC
RC
-V
P r e l i m i n a r y
- 0.2, CS2 ≥ V
+3t
IH
IN
CC
≤0.2V or V
or V
IH
C
PC
L
, I
LB#=V
IL
IO
Test Conditions
=0mA, 100% duty,
IL
CC
IN
IO
and/or
≥VCC-0.2V
- 0.2V (CS1# controlled) or
=0mA,
CC
(64Mb,
SB1
pSRAM_15_A2 February 3, 2005
Min Typ Max Unit
is measured after 60ms
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TBD
TBD
TBD
mA
mA
µA