S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 53

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

11 Power Conservation Modes
11.1
11.2
11.3
11.4
November 23, 2005 S29PL-N_M0_A4
Standby Mode
Automatic Sleep Mode
Hardware RESET# Input Operation
Output Disable (OE#)
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at V
cess time (t
erasure or programming, the device draws active current until the operation is completed. I
DC Characteristics
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t
The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when addresses are changed. While in sleep mode, out-
put data is latched and always available to the system. I
automatic sleep mode current specification.
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V
is held at V
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
When the OE# input is at V
high impedance state.
IL
CE
but not within V
) for read access, before it is ready to read data. If the device is deselected during
represents the standby current specification
P r e l i m i n a r y
S29PL-N MirrorBit™ Flash Family
SS
IH
±0.2 V, the device draws CMOS standby current (I
SS
, output from the device is disabled. The outputs are placed in the
±0.2 V, the standby current is greater.
CC
RP
, the device immediately terminates any
±0.2 V. The device requires standard ac-
CC6
in
DC Characteristics
CC4
represents the
). If RESET#
ACC
+ 20 ns.
CC3
51
in