S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 67

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

November 23, 2005 S29PL-N_M0_A4
Addresses
Note:
data read cycle
Note:
status read cycle, and array data read cycle
Addresses
DQ6–DQ0
DQ6/DQ2
RY/BY#
RY/BY#
CE#
WE#
DQ7
OE#
WE#
OE#
CE#
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
Valid Data
Figure 13.13 Data# Polling Timings (During Embedded Algorithms)
t
t
BUSY
CH
Figure 13.14 Toggle Bit Timings (During Embedded Algorithms)
t
DH
t
t
OEH
OEH
P r e l i m i n a r y
t
ACC
t
S29PL-N MirrorBit™ Flash Family
CE
t
VA
t
RC
OE
(first read)
Status
Valid
Complement
Status Data
t
OEPH
t
OH
t
DF
t
AHT
t
OE
(second read)
t
ASO
Status
Valid
VA
Complement
Status Data
t
CEPH
t
t
AHT
AS
True
True
(stops toggling)
Status
Valid
VA
Valid Data
Valid Data
Valid Data
High Z
High Z
65