ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 99

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.7.10
CPU Address:h609
Accessed by CPU (R/W)
13.3.7.11
CPU Address:h60A
Accessed by CPU (R/W)
13.3.7.12
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
This register is used in unmanaged mode only. Before requesting that the ZL50408 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
The checksum formula is:
When the ZL50408 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50408 does not start and pin CHECKSUM_OK is set to zero.
Bits[5:0]:
Bits[7:6]:
Bit [0]:
Bit [1]:
Bit [4:2]:
Bit [7:5]:
Bit [7:0]:
DEVICE Mode
USD – One Micro Second Divider
CHECKSUM - EEPROM Checksum
FF
Σ
i = 0
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1usec for internal reference.
Reserved
0: Negative Polarity
1: Positive Polarity (Default)
DEVICE ID (Default 0). This is for stacking operation. This is the stack ID for
loop topology.
Checksum content (Default 0)
Reserved
CPU Interrupt Polarity
Reserved
I²C register = 0
Zarlink Semiconductor Inc.
ZL50408
99
Data Sheet