ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
ZL50408GDC
Manufacturer Part Number
ZL50408GDC
Description
Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50408GDC.pdf
(132 pages)
- Current page: 24 of 132
- Download datasheet (2Mb)
4. Lightly Managed Serial. Configuration registers access, Control frame and CPU transmit/receive packets are
5. Unmanaged Serial. The device can be configured by EEPROM using an I²C interface at bootup, or via a syn-
The CPU interface provides for easy and effective management of the switching system.
Figure 3 on page 24 provides an overview of the 8/16-bit interface. Figure 4 on page 25 provides an overview of the
SSI interface. Figure 5 on page 26 provides an overview of the SSI+MII interface.
sent through a synchronous serial interface (SSI) bus.
chronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible
by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt informa-
tion.
Index Reg 1
(Addr = 1)
16-bit Address
Index Reg 0
(Addr = 0)
8-bit Data Bus
Config Data
(Addr = 2)
Registers
Inderect
Internal
Access
Reg
Figure 3 - Overview of the 8/16-bit Interface
3-bit Address Bus
CPU Frame Reg
8/16-bit Data Bus
Processor
CPU frame
Address
Receive
(Addr = 3)
Zarlink Semiconductor Inc.
FIFO
CPU frame
ZL50408
Transmit
FIFO
24
8/16-bit Data Bus
Command/
Status Reg
(Addr = 4)
I/O Data MUX
Interrupt
(Addr = 5)
Interrupt
Reg
8/16-bit Data Bus
Command 1
Receive
Control
FIFO
Command 1 Reg
(Addr = 6)
Control
Command 1
Transmit
Control
FIFO
Data Sheet
Command 2
Command 2
(Addr = 7)
Transmit
Control
Control
FIFO
Reg
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