ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 23

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.5
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment, and trunking functions.
2.6
The ZL50408 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet
generation module allows simultaneous tracking of all the RMAC ports.
Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time
period, If a reply is not received in a specified amount of time, the failover detection module will identify a
point-to-point failure for that link. The failover detection module will then interrupt the CPU.
The LHB packet response module can also reply to LHB messages initiated by other ZL50408 devices in the
system, or by non-ZL50408 devices which use a conventional and recognizable LHB message format.
2.7
The ZL50408 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine
is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin
(TSTOUT12). It also requires some register configuration via the CPU interface.
See Programming Timeout Reset application note, ZLAN-41, for more information.
2.8
An IEEE1149.1 compliant test interface is provided for boundary scan.
3.0
One extra port is dedicated to the CPU via the CPU interface module. Three modes this port can operate:
managed, lightly managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame, tx/rx
control frame and receiving interrupt due to the lack of constant attention or processing power from the CPU.
The CPU interface utilizes a 8/16-bit bus in managed mode. It also supports a serial+MII, serial only, and an I
interface, which provides an easy and lower cost way to configure the system for reduced management.
Supported CPU interface modes are
1. 16-bit CPU interface similar to the Industry Standard Architecture (ISA) specification.
2. 8-bit CPU interface similar to ISA.
3. Serial with MII. A synchronous serial interface (SSI) bus is used for accessing the configuration register and
16-bit CPU
8-bit CPU
Serial with MII interface
Lightly Managed Serial
Unmanaged Serial
control frame. MII is used for sending and receiving CPU packets.
Search Engine
Heartbeat Packet Generation and Response
Timeout Reset Monitor
JTAG
Management and Configuration
Operation Mode
Table 6 - Supported CPU interface modes
16-bit
8-bit
NA
NA
NA
ISA Interface
Zarlink Semiconductor Inc.
ZL50408
23
NA
NA
Yes
Yes
Yes
Serial
NA
NA
Yes
No
No
MII
NA
NA
No
No
Yes
Data Sheet
I²C
2
C