ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 47

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

cable, the destination port in Device B, and loop back to itself, back to the cable and go back to Device A and the
CPU. This way, the whole channel can be tested.
10.0
10.1
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR register. Only
port-based VLAN is supported with GPSI interface.
11.0
11.1
11.1.1
SCLK is the primary clock for the ZL50408 device. The speed requirement is based on the system configuration.
Below is a table for a few configuration.
11.1.2
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-7) and CPU port (port 8).
If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be
applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal
1usec timing.
11.1.3
GREF_CLK is a 125 MHz reference clock required for the GMAC port (port 9).
If the device is in a 9 port 10/100 configuration only, GREF_CLK can be a lower frequency clock and can be
connected to M_CLK to reduce the number of clock sources.
8 Port 10/100M + 1 port 1000M
6-9 ports 10/100M
1-5 ports 10/100M
Clock Requirements
GPSI connection
Clocks
GPSI (7WS) Interface
RMAC Reference Clock (M_CLK) speed requirement
GMAC Reference Clock (GREF_CLK) speed requirement
System Clock (SCLK) speed requirement
DEVICE A
CPU
Configuration
Table 12 - SCLK Speed Requirements
Figure 12 - Remote Loopback Test
Zarlink Semiconductor Inc.
ZL50408
47
100 MHz
50 MHz
25 Mhz
Minimum SCLK speed
DEVICE B
required
Data Sheet