ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 22

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.2.2
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary
interface TX and RX clocks to the CPU, or a register access mechanism via the 8/16-bit or serial interface.
Using the MII interface, the CMAC of the ZL50408 device meets the IEEE 802.3 specification. It is able to operate
in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 8.
2.2.3
The GMII Media Access Control (GMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface,
which offers a simple migration from 10/100 to 1G.
The GMAC of the ZL50408 device meets the IEEE 802.3Z specification. It is able to operate in 10M/100M either
Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 9. The PHY address for the PHY device connected to the GMAC port has to be 10h.
2.2.4
The table below provides an overview of the PHY addresses required for each port in order for the MDIO
auto-negotiation to work between the ZL50408 MAC and the PHY device. If a different PHY address is used, then
the port must be manually brought up and the PHY will need to be polled for link status via the MIIC/D registers.
2.3
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
This module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device.
2.4
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the
search engine, to resolve the destination port. The arriving frame is moved to the internal memory. After receiving a
switch response from the search engine, the frame engine performs transmission scheduling based on the frame’s
priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
Management Module
Frame Engine
CPU MAC Module (CMAC)
GMII MAC Module (GMAC)
PHY Addresses
RMAC Port 0
RMAC Port 1
...
RMAC Port 7
CMAC Port 8
GMAC Port 9
MAC Port
Table 5 - PHY Addresses
Zarlink Semiconductor Inc.
ZL50408
22
PHY Address
0x08
0x09
...
0x0F
NA
0x10
Data Sheet