ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet - Page 70

• Manufacturer Part Number: ZL50060
• Description: 16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.9
Addresses 00A3
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31.
For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal
system clock (131.072 MHz).
The BOAR0 to BOAR31 registers are configured as follows:
14.9.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
(where n = 0 to 31 for Backplane
Non-32 Mbps Mode, n = 0 to 15
for Backplane 32 Mbps Mode)
Backplane Output Advancement For
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
Local Output Advancement For
Backplane Output Advancement Registers (BOAR0 - BOAR31)
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
BOARn Bit
Clock Rate 131.072 MHz
Clock Rate 131.072 MHz
Table 31 - Local Output Advancement (LOAR) Programming Table (continued)
15:2
1:0
-4 cycles (~31 ns)
-6 cycles (~46 ns)
-2 cycles (~15 ns)
-4 cycles (~31 ns)
-6 cycles (~46 ns)
H
Table 33 - Backplane Output Advancement (BOAR) Programming Table
to 00C2
0 (Default)
Table 32 - Backplane Output Advancement Register (BOAR) Bits
H
Reserved
BOA[1:0]
Name
Zarlink Semiconductor Inc.
ZL50060/1
Reset
Value
0
0
Advancement For 32 Mbps
Advancement For 32 Mbps
70
Clock Rate 131.072 MHz
Clock Rate 131.072 MHz
Backplane Output
-2 cycles (~15 ns)
-3 cycles (~23 ns)
-2 cycles (~15 ns)
-3 cycles (~23 ns)
-1 cycle (~7.6 ns)
Reserved
Must be set to 0 for normal operation
Backplane Output Advancement Value
Local Output
0 (Default)
Description
Advancement Bits
Advancement Bits
BOA1
LOA1
Corresponding
Corresponding
1
1
0
0
1
1
Data Sheet
BOA0
LOA0
0
1
0
1
0
1