ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet - Page 19

• Manufacturer Part Number: ZL50060
• Description: 16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
JTAG Control Signals
Power and Ground Pins
Pin Name
V
RESET
DD_CORE
V
TRST
TMS
TCK
TDo
DD_IO
TDi
D6, D11, D15,
L17, R4, R17,
D14, K1, K20,
N3, P18, T17,
U6, U10, U15
Coordinates
Y7, Y11, Y14
A7, B4, B12,
U16, V1, V5,
F4, F17, K4,
ZL50061
Package
(272-ball
PBGA)
C12
D12
C13
A14
B13
B14
E12, F5, F12,
H12, L5, L12,
E10, F6, F11,
Coordinates
G5, G12, H5,
E5, E6, E11,
K12, L6, L7,
J5, J12, K5,
E7, E8, E9,
Package
(256-ball
ZL50060
M5, M12
L10, L11
PBGA)
D10
B12
C12
B11
C11
D11
Zarlink Semiconductor Inc.
ZL50060/1
Test Reset (5 V Tolerant Input with Internal Pull-up).
Asynchronously initializes the JTAG TAP controller to the
Test-Logic-Reset state. This pin must be pulsed LOW during
power-up for JTAG testing. This pin must be held LOW for
normal functional operation of the device.
Power Supply for Periphery Circuits: +3.3 V
Device Reset (5 V Tolerant Input with Internal Pull-up).
This input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of
RESET causes the LCSTo0-3 and BCSTo0-3 pins to be driven
LOW (refer to Table 2). The assertion of this pin also clears
the device registers and internal counters. Refer to
Section 8.3 on page 47 for the timing requirements
regarding this reset signal.
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test logic.
Test Mode Select (5 V Tolerant Input with Internal Pull-up).
JTAG signal that controls the state transitions of the TAP
controller.
Test Serial Data In (5 V Tolerant Input with Internal
Pull-up).
JTAG serial test instructions and data are shifted in on this pin.
Test Serial Data Out (5 V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
Power Supply for Core Circuits: +1.8 V
19
Description
Data Sheet