ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet - Page 68

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ZL50060

Manufacturer Part Number
ZL50060
Description
16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
14.7.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7
period. The default sampling point is at the
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from
Table 29 illustrates the bit delay and sampling point selection.
Backplane Input Delay Bits 4-0 (BID[4:0])
BID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table
BID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
BIDn
BID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
/
3
4
/
4
to
Zarlink Semiconductor Inc.
bit location.
4
ZL50060/1
/
BID0
4
in
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
/
4
68
-bit increments.
SMPL_MODE
Input Data
0 (Default)
Bit Delay
= LOW
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
1/4
1/2
3/4
1
2
3
4
5
6
3
/
4
bit periods forward, with resolution of
1
/
4
= 4
Input Data
3
0 (Default)
Bit Delay
/
4.
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
SMPL_MODE
= HIGH
Input Data
Sampling
Point
1
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
/
4
to
Data Sheet
4
/
4
). BID[4:2]
1
/
4
bit

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