ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 31

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
SRTXK_VSYNC_SEL
SRTXK_VSYNC_THR_L
SRTXK_VSYNC_THR_H
SRTXK_COAST_VS_SEL
SRTXK_COAST_RISE_L
SRTXK_COAST_RISE_M
SRTXK_COAST_RISE_H
SRTXK_COAST_FALL_L
SRTXK_COAST_FALL_M
SRTXK_COAST_FALL_H
SRTIK_HS_CTRL
SRTIK_VS_SEL
Register Name
Table 12: Sync Retiming Registers (Sheet 2 of 2)
0x01E5
0x01E7
0x01E8
0x01EA
0x01EB
0x01EC
0x01ED
0x01EE
0x01F0
0x01F1
0x01E6
0x01E9
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7:3]
[2:0]
[7:0]
[7:4]
[3:0]
[7:4]
[3]
[2:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[2]
[1:0]
[7:2]
[1:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x080
0x0
0x0
0x0
0x0
0x0
0x0
Default
Reserved
filtered vert sync source select
0x0: avsync pin
0x1: vsync from composite ahsync pin
0x2: vsync from composite acsync pin
0x3: Reserved
0x4: DVI vsync
0x5: YUV vsync
0x6 - 0x7: Reserved
Reserved
filtered vert sync delay [11:8]
coast signal trigger edge
0: posedge of selected vertical
1: negedge of selected vertical
source select for coast vert sync trigger
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: Reserved
0x4: DVI vsync
0x5: YUV vsync
0x6: srt vsync (filtered vsync)
0x7: Reserved
trigger
falling edge of coast, in XCLKs from vsync
trigger
Reserved
Resample clock edge to transfer hsync into
the INCLK domain; depends on LLK phase
offset value.
0: posedge INCLK
1: negedge INCLK
horz sync source select for resampling into
the INCLK domain
0x0: LLPLL lock sync (normal)
0x1: ahsync pin
0x2: acsync pin
0x3: Reserved
Reserved
vert sync source select for resampling
0x0: avsync pin
0x1: vsync from ahsync pin
0x2: vsync from acsync pin
0x3: srt vsync (filtered vsync)
filtered vert sync delay [7:0]
Reserved
rising edge of coast, in XCLKs from vsync
Description
Sync Retiming Block
31/88