ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 22

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Digital Video Input (DVI)
22/88
2.5
LLK_PLL_UPDATE
LLK_PLL_STATUS
LLK_PLL_PH_ERROR_L
LLK_PLL_PH_ERROR_H
LLK_PLL_PHASE_RATE_0
LLK_PLL_PHASE_RATE_1
LLK_PLL_PHASE_RATE_2
LLK_PLL_PHASE_RATE_3
LLK_PLL_PHASE_RATE_I_0
LLK_PLL_PHASE_RATE_I_1
LLK_PLL_PHASE_RATE_I_2
LLK_PLL_PHASE_RATE_I_3
LLK_PLL_STAT_ERROR_MEAN
LLK_PLL_STAT_ERROR_PP_L
LLK_PLL_STAT_ERROR_PP_H
LLK_PLL_STAT_ERROR_ABS_L
LLK_PLL_STAT_ERROR_ABS_H
LLK_PLL_STAT_ERROR_GTX
Digital Video Input (DVI)
The DVI receiver has the following features:
Register Name
compatible with all DVI complaint transmitters up to 140 MHz pixel clock
on chip termination adjustable by I2C and/or one (~10X) external reference resistor
HDCP and standby / power down supported
decoder digitally corrects for skew errors of at least ±1 pixel in reference to any other channel
bitstream can be decoded and measured without the presence of horizontal and vertical sync
pulses
Table 7: Line Lock PLL Registers (Sheet 4 of 4)
0x0840
0x0841
0x0842
0x0843
0x0844
0x0845
0x0846
0x0847
0x0848
0x0849
0x084A
0x084B
0x084C
0x084D
0x084E
0x084F
0x0850
0x0851
Addr
R
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Mode
[7]
[6:2]
[1]
[0]
[7:4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits
0x0
0x0
Default
is updated.
In one-shot mode, this bit is set when status
is ready.
Reserved
0: Free-running mode
1: one-shot mode
update enable
Reserved
LLK overflow
coarse error = 0
in slow mode
in lock mode
f
phase error LSB is approx. 200ps
STAT_LINES
phase error LSB is approx. 200ps
In Free-running mode, toggles when status
phase error
LSB = approx. 200ps
LLK phase rate
integral phase rate
Average Phase Error over STAT_LINES
Peak Phase Error over STAT_LINES
phase error LSB is approx. 200ps
sum of absolute phase errors over
Reserved
OUT
= f
XTAL
x 2
Description
27+NDIV
/ PHASE_RATE
ADE3XXX