EVAL-AD5383EB AD [Analog Devices], EVAL-AD5383EB Datasheet - Page 33

• Manufacturer Part Number: EVAL-AD5383EB
• Description: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
• Manufacturer: AD [Analog Devices]

APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5383 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5383 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only, a star ground
point established as close to the device as possible.
For supplies with multiple pins (AV
be tied together. The AD5383 should have ample supply bypas-
sing of 10 µF in parallel with 0.1 µF on each supply, located as
close to the package as possible and ideally right up against the
device. The 10 µF capacitors are the tantalum bead type. The
0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.
The power supply lines of the AD5383 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the D
between them (this is not required on a multilayer board
because there will be a separate ground plane, but separating the
lines will help). It is essential to minimize noise on the V
REFIN lines.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but is not always possible with
a double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the solder side.
TYPICAL CONFIGURATION CIRCUIT
Figure 39 shows a typical configuration for the AD5383-5 when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied
together to a common AGND. AGND and DGND are
connected together at the AD5383 device. On power-up, the
AD5383 defaults to external reference operation. All AV
are connected together and driven from the same 5 V source. It
is recommended to decouple close to the device with a 0.1 µF
ceramic and a 10 µF tantalum capacitor. In this application, the
reference for the AD5383-5 is provided externally from either
IN
and SCLK lines will help reduce crosstalk
DD
, DV
DD
), these pins should
DD
IN
and
lines
Rev. 0 | Page 33 of 40
an ADR421 or ADR431 2.5 V reference. Suitable external
references for the AD5383-3 include the ADR280 1.2 V
reference. The reference should be decoupled at the
REFOUT/REFIN pin of the device with a 0.1 µF capacitor.
Figure 40 shows a typical configuration when using the internal
reference. On power-up, the AD5383 defaults to an external
reference; therefore, the internal reference needs to be
configured and turned on via a write to the AD5383 control
register. Control Register Bit CR10 allows the user choose the
reference value; Bit CR 8 is used to select the internal reference.
It is recommended to use the 2.5 V reference when AV
and the 1.25 V reference when AV
Digital connections have been omitted for clarity. The AD5383
contains an internal power- on reset circuit with a 10 ms
brownout time. If the power supply ramp rate exceeds 10 ms,
the user should reset the AD5383 as part of the initialization
process to ensure the calibration data gets loaded correctly into
the device.
ADR431/
ADR421
0.1µF
Figure 39. Typical Configuration with External Reference
Figure 40. Typical Configuration with Internal Reference
0.1µF
REFOUT/REFIN
REFGND
AVDD
AVDD
REFOUT/REFIN
REFGND
GND
DAC
0.1µF
AVDD
AVDD
10µF
DAC
GND
SIGNAL
GND
AD5383
0.1µF
10µF
SIGNAL
GND
AD5383-5
AGND
DD
= 3 V.
AGND
DVDD
DGND
DVDD
VOUT31
VOUT0
DGND
DVDD
DVDD
0.1µF
VOUT31
VOUT0
0.1µF
AD5383
DD
= 5 V,