EVAL-AD5383EB AD [Analog Devices], EVAL-AD5383EB Datasheet - Page 10

• Manufacturer Part Number: EVAL-AD5383EB
• Description: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
• Manufacturer: AD [Analog Devices]

AD5383
I
Table 7. DV
T
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
2
Guaranteed by design and characterization, not production tested.
See Figure 6.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
falling edge.
C
SCL
b
MIN
3
SDA
C SERIAL INTERFACE TIMING
SCL
b
is the total capacitance, in pF, of one bus line. t
to T
MAX
1, 2
DD
, unless otherwise noted
t
9
= 2.7 V to 5.5 V; AV
CONDITION
START
t
4
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1C
400
t
3
b
MIN
4
DD
, T
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
MAX
t
R
10
and t
t
6
Figure 6. I
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
F
are measured between 0.3DV
2
C Compatible Serial Interface Timing Diagram
t
2
Rev. 0 | Page 10 of 40
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
t
11
, bus free time between a STOP and a START condition
, SCL low time
, SCL high time
, setup time for repeated start
, start/repeated start condition hold time
, data setup time
, stop condition setup time
t
, data hold time
, data hold time
5
DD
and 0.7DV
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
DD
.
CONDITION
REPEATED
START
t
7
t
4
t
1
CONDITION
STOP
t
8