EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet
EVAL-AD1896EB
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EVAL-AD1896EB Summary of contents
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... AD1896 output port is operating in 512 × f then the master clock is divided by two. The 256 f DAC) is divided by two to generate the 128 f SPDIF transmitter. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 EVAL-AD1896EB , and 128 f (Figure 9 of the AD1896EB S S master mode, S ...
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... EVAL-AD1896EB The following section highlights key jumpers and switches on the evaluation board. Please refer to the AD1896 evaluation board schematic for more details. These switches and jumpers configure the AD1896 and other components, such as, SPDIF receiver, transmitter, and stereo DAC. SWITCH AND JUMPER FUNCTIONS • ...
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... Input Serial Port is Master with 768 Input Serial Port is Master with 512 *Input Serial Port is Master with 256 EVAL-AD1896EB S4 (8-POSITION SWITCH) DDO-HDR5, SPDIF-J2, TDM_OUT-HDR2 TDM IN HEADER HDR1 JP1 (4-POSITION JUMPER) HDR3 (DDI) HDR5 (DDO ( (O) SDATA_I (I) ...
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... EVAL-AD1896EB Switch SW4 f f S_IN S_OUT 0 132.3 kHz Set Externally 1 66.15 kHz Set Externally 2 44.1 kHz Set Externally 3 Not Used Not Used 4 Set Externally 132.3 kHz 5 Set Externally 66.15 kHz 6 Set Externally 44.1 kHz 7 Set Externally Set Externally S3 Switch Position DIGITAL AUDIO OUTPUT SIGNALS ...
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... J1, U4) J2) DIRECT X SPDIF INPUT X TDM_IN DIRECT OUTPUT SPDIF TDM_OUT TOSLINK Group Delay Bypass Mode (S8) (S6) Short X Enable Long Disable EVAL-AD1896EB ~250 ~300 mA–360 AD1896 AP2 RECEIVER SCLK SCLK_I SCLK_O SCLK LRCLK LRCLK_I LRCLK_O LRCLK SDATA SDATA_I SDATA_O SDATA Group ...
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... S 2. AD1896 Evaluation Board Block Diagram, Schematics, and Layout Plots 3. Bill of Materials 4. PLD Code FURTHER INFORMATION Ordering Information Order number is EVAL-AD1896EB For Application Questions or Technical Support Contact Analog Devices’ Central Applications Department at 1-781-937-1428 for assistance. AD1852 DAC U12 LEFT OUT ...
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... JUMPER JP4, MCLK_SRCE PINS 1 AND 2 5. JUMPER JP1, O/P I/F MODE POSITIONS 1, 2, AND 4 FOR 24-BIT I 6. JUMPER JP2, SELECT POSITION 1 ONLY FOR 192kHz DAC OPERATION 7. SET S1 TO DIR 8. SET S2 TO SELECT COAX OR OPTICAL INPUT Q0 Q1 LRCLK Q2 192kHz Q3 EVAL-AD1896EB 5V J1 HEADER10 OUTPUT ...
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... ALL ELECTROLYTIC CAPACITORS ARE 20 (OR HIGHER), ALUMINUM ELECTROLYTE TYPES. 3.9 ALL T CAPACITORS ARE 20 (OR HIGHER), TANTALUM ELECTROLYTE TYPES FOR COMPLETE INFORMATION ON ANY COMPONENT, PLEASE SEE THE ASSOCIATED BILL OF MATERIALS. 5. ALL NET NAMES PRECEDED BY/ARE ACTIVE LOW SIGNALS. EVAL-AD1896EB SAMPLE RATE CONVERTER 96-040C.SCH TDM-I SDATA-O SDATA-I ...
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... EVAL-AD1896EB Item Qty Ref Detail 1 1 LH99321 Rev U12 AD1852JRS 3 1 U13 AD1895YRS ADM811TART ADP3303AR-3 U10 ADP3303AR CS8404A- CS8414- LM317MDT 10 2 U2, U3 M4A5-64/32-10VC 11 1 U11 OP275GS 12 1 U14 74AHC02 13 2 U17, U18 74AHC74 ...
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... Switch Slide DPDT Side Act PCB Switch Rotary 8 Pos Octal Switch PB NO Momentary Tactile Switch Slide SPDT Vert Act PCB IC Fiber Optic Receiver Connector Binding Post Connector Binding Post Connector Binding Post Spacer Nylon 3/4" Snap-In EVAL-AD1896EB Mfr P/N Mfr Name 2380-6121TN 3M 2380-6121TN 3M 51138-44624 3M ...
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... EVAL-AD1896EB MODULE IF_Logic TITLE 'AD1896 EVB Input Interface Logic' //=================================================================================== // FILE: input_pld.abl // REVISION DATE: 03-20-01 // REVISION BY: Chirag Patel // REVISION: 1 DESCRIPTION This input interface PLD (U2) selects between the External Data Interface header // (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending // upon the SPDIF/DDI switch position (S1) ...
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... RJ24 # RJ20 # I2S) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M1 = ((I2S # RJ18) & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256)) # (I2S & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M2 = RJ18 # RJ16 node istype 'com'; in_pld.abl IN_MODE1 & IN_MODE0); IN_MODE1 & !IN_MODE0); !IN_MODE1 & IN_MODE0); !IN_MODE1 & !IN_MODE0); IN_MODE1 & IN_MODE0); IN_MODE1 & !IN_MODE0); EVAL-AD1896EB ...
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... EVAL-AD1896EB // IO control logic DDI_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); DDI_LRCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); DIR_FSYNC.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); DIR_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); SCLK_I.oe = (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); LRCLK_I.oe = (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); DDI_SCLK = ISCLK; DDI_LRCLK = ILRCLK; DIR_SCLK = ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S); ...
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... I_SDATA, ISCLK, ILRCLK //================================================================================ "MACROS out_pld.abl On the other hand, these signals are pro- //JTAG I/P's pin 21, 20 istype 'com'; //JTAG O/P pin 11, 10 istype 'com'; pin 14,12, 13, 15 istype 'com'; pin 36, 35 istype 'com, buffer'; pin 23, 24 istype 'com, buffer'; node istype 'com, buffer'; out_pld.abl EVAL-AD1896EB ...
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... EVAL-AD1896EB //OUTPUT SERIAL DATA FORMATS // JP1[4:3] 0, LEFT-JUSTIFIED LJ = (!OPMODE1 & !OPMODE0); // JP1[4:3] 1, I2S I2S = (!OPMODE1 & OPMODE0); // JP1[4:3] 2, TDM MODE TDM = (OPMODE1 & !OPMODE0); // JP1[4:3] 3, RIGHT-JUSTIFIED RJ = (OPMODE1 & OPMODE0); // OUTPUT DATA BIT WIDTH SETTINGS // JP1[2:1] 0, 24-BITS BITS_24 = ( !WDLNGTH1 & !WDLNGTH0); // JP1[2:1] 0, 20-BITS ...
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... DDO_LRCLK = ILRCLK; SCLK_O = ISCLK; LRCLK_O = ILRCLK; // DAC AND DIT SIGNALS SDATA_DAC_DIT = SDATA_O; LRCLK_DAC = ILRCLK; The chip is configured in the LJ mode when AD1896 output Also need to invert the incoming SCLK signal in the NOTE that the DAC requires serial Based on the Master/Slave operation of the EVAL-AD1896EB ...
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... EVAL-AD1896EB SCLK_DAC = ISCLK; FSYNC_DIT = ILRCLK; SCLK_DIT = ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) // Internal node signals ISCLK = ((SCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_SCLK) & (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); ILRCLK = ((LRCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (LJ # TDM # RJ24 # RJ20 # RJ18 # RJ16)) # ((!DDO_LRCLK) & ...
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