EVAL-AD5383EB AD [Analog Devices], EVAL-AD5383EB Datasheet - Page 31

• Manufacturer Part Number: EVAL-AD5383EB
• Description: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
• Manufacturer: AD [Analog Devices]

MICROPROCESSOR INTERFACING
Parallel Interface
The AD5383 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5383 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0–A4 on the AD5383. The upper address lines are decoded to
provide a CS , LDAC signal for the AD5383. The fast interface
timing of the AD5383 allows direct interface to a wide variety of
microcontrollers and DSPs, as shown in Figure 35.
AD5383 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5383, the MOSI output drives the serial data line (D
of the AD5383, and the MISO input is driven from D
SYNC signal is derived from a port line (PC7). When data is
DSP PROCESSOR*
µCONTROLLER/
UPPER BITS OF
ADDRESS BUS
DATA
BUS
R/W
D15
D0
A4
A3
A2
A1
A0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. AD5383-to-Parallel Interface
OUT
. The
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IN
)
ADDRESS
DECODE
being transmitted to the AD5383, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle.
MC68HC11
REG1
REG0
D11
D0
CS
LDAC
A4
A3
A2
A1
A0
WR
MISO
MOSI
SCK
PC7
Figure 34. AD5383-to-MC68HC11 Interface
AD5383
DV
DD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I2C
AD5383
AD5383