EVAL-AD5383EB AD [Analog Devices], EVAL-AD5383EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD5383EB
• Description: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
• Manufacturer: AD [Analog Devices]

GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit
DAC available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference, an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring, and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
contains a double-buffered parallel interface that features a
20 ns WR pulse width, an SPI/QSPI/MICROWIRE/DSP
compatible serial interface with interface speeds in excess of
Table 1. Other High Channel Count, Low Voltage, Single Supply DAC Products in Portfolio
Model
AD5380BST-5
AD5380BST-3
AD5384BBC-5
AD5384BBC-3
AD5381BST-5
AD5381BST-3
AD5382BST-5
AD5382BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
Table 2. 40-Channel, Bipolar Voltage Output DAC
Model
AD5379ABC
Resolution
14 Bits
Resolution
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
Analog Supplies
±11.4 V to ±16.5 V
AV
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
DD
Range
Output Channels
40
40
40
40
40
40
32
32
16
16
16
16
16
16
16
16
8
8
8
8
Output Channels
40
Rev. 0 | Page 3 of 40
Linearity Error (LSB)
±4
±4
±4
±4
±1
±1
±4
±4
±3
±3
±3
±3
±1
±1
±1
±1
±3
±3
±3
±3
Linearity Error (LSB)
±3
30 MHz, and an I
400 kHz data transfer rate.
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen-
dently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
Power consumption is typically 0.25 mA/channel with boost
off.
2
C compatible interface that supports a
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package
108-Lead CSPBGA
Package Option
Package Option
BC-108
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
AD5383