EVAL-AD5383EB AD [Analog Devices], EVAL-AD5383EB Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD5383EB
• Description: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
• Manufacturer: AD [Analog Devices]

Mnemonic
MON_OUT
MON_INx
SER/PAR
CS/(SYNC/AD0)
WR/(DCEN/ AD1)
DB11–DB0
A4–A0
REG1, REG0
SDO/(A/B)
BUSY
LDAC
CLR
RESET
Function
When the monitor function is enabled, this output acts as the output of a 36-to-1 channel multiplexer that can be
programmed to multiplex one of Channels 0 to 31or any of the monitor input pins (MON_IN1 to MON_IN4) to the
MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω, and is intended to drive a high input
impedance like that exhibited by SAR ADC inputs.
MON_IN Monitor Input Pins. The AD5383 contains four monitor input pins that allow the user to connect input
signals within the maximum ratings of the device to these pins for monitoring purposes. Any of the signals applied
to the MON_IN pins along with the 32 output channels can be switched to the MON_OUT pin via software. An
external ADC for example can be used to monitor these signals.
Interface Select Input. This pin allows the user to select whether the serial or parallel interface will be used. If it is tied
high, the serial interface mode is selected and Pin 97 (SPI/I2C) is used to determine if the interface mode is SPI or I
Parallel interface mode is selected when SER/PAR is low.
In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5383 is
selected.
Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed
register is updated.
I
for the device on the I
Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a
daisy-chain enable in SPI mode and as a hardware address pin in I
Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low and the
address bus inputs to write to the selected device registers.
Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction
with SER/PAR high to enable the SPI serial interface Daisy-Chain mode.
I
for this device on the I
Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5383.
Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5383’s 40 input channels. Used in conjunction
with the REG1 and REG0 pins to determine the destination register for the input data.
In parallel interface mode REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and
REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are
also used to decide the special function registers.
Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a
number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge
of SCLK.
When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the
AD5383’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the
LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels
contain two data registers. In normal mode, Data Register A is the default for data transfers.
Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.
During this time, the user can continue writing new data to the x1, c, and m registers in parallel mode (these are
stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low
while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the BUSY pin is low.
During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY
low.
Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input
registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated
with the data contained in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being
updated with the CLR code.
Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-
on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1,
m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET
initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY
is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal
operation and the status of the RESET pin is ignored until the next falling edge is detected.
2
2
C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address
C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address
2
2
C bus.
C bus.
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2
C mode.
AD5383
2
C.