AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 44

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

42
erase suspended,
actively erasing,
programming in
erase suspend
programming,
If device is
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to
See the following for additional information:
page 41, See “DQ6: Toggle Bit I” on page 40., Figure 28, “Toggle Bit Timings
(During Embedded Algorithm),” on page
cations,” on page
Refer to Figure 4 for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 4).
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed.
at an address within sectors not
at an address within sectors not
at an address within a sector
at an address within a sector
and the system reads
selected for erasure,
selected for erasure,
selected for erasure,
selected for erasure,
at any address,
at any address,
42.
Table 14. DQ6 and DQ2 Indications
Table 14
Am29BDS640G
P r e l i m i n a r y
to compare outputs for DQ2 and DQ6.
returns array data,
does not toggle,
65, and
then DQ6
toggles,
toggles,
toggles,
toggles,
Figure 5, “Toggle Bit Algorithm,” on
Table 14, “DQ6 and DQ2 Indi-
from any sector not selected for erasure.
returns array data. The system can read
is not applicable.
does not toggle.
does not toggle.
also toggles.
and DQ2
toggles.
25903C1 October 1, 2003