AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 34

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

32
Program Command Sequence
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin.
data requirements for the program command sequence.
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the
“Write Operation Status” section on page 38
tus bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program op-
eration. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit can-
not be programmed from “0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the oper-
ation was successful. However, a succeeding read will show that the data is still
“0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to a bank
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
Manufacturer ID
Device ID, Word 1
Device ID, Word 2
Device ID, Word 3
Sector Block
Lock/Unlock
Handshaking
Description
Am29BDS640G
(BA) + 00h
(BA) + 01h
(BA) + 0Eh
(BA) + 0Fh
(SA) + 02h
(BA) + 03h
Address
P r e l i m i n a r y
section for information on these sta-
Table 13
2224h (1.8 V V
2234h (3.0 V V
2204h (1.8 V V
2214h (3.0 V V
43h (reduced wait-state),
0000 (unlocked)
42h (standard)
0001 (locked),
shows the address and
Read Data
0001h
227Eh
2201h
IO
IO
, bottom boot),
IO
IO
, bottom boot)
, top boot),
, top boot),
25903C1 October 1, 2003