AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 19

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

October 1, 2003 25903C1
Output Disable Mode
Hardware Data Protection
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
RESET# may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires
a time of t
data again. If RESET# is asserted when a program or erase operation is not ex-
ecuting, the reset operation is completed within a time of t
Embedded Algorithms). The system can read data t
V
Refer to the AC Characteristics tables for RESET# parameters and to
“Reset Timings,” on page 57
When the OE# input is at V
placed in the high impedance state.
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to
Definitions,” on page 37
The device offers two types of data protection at the sector level:
The following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during V
Write Protect (WP#)
The Write Protect (WP#) input provides a hardware method of protecting data
without using V
If the system asserts V
functions in sectors 0 and 1 (bottom boot) or sectors 132 and 133 (top boot).
If the system asserts V
outermost 8K Byte boot sectors were last set to be protected or unprotected.
Note that the WP# pin must not be left floating or unconnected; inconsistent be-
havior of the device may result.
Low V
When V
tects data during V
internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
IH
.
The sector lock/unlock command sequence disables or re-enables both pro-
gram and erase operations in any sector.
When WP# is at V
(top boot) are locked.
When ACC is at V
SS
IL
but not within V
± 0.2 V, the device draws CMOS standby current (I
CC
CC
CC
READY
is less than V
Write Inhibit
power-up and power-down transitions, or from system noise.
ID
(during Embedded Algorithms) before the device is ready to read
.
CC
P r e l i m i n a r y
IL
IL
power-up and power-down. The command register and all
SS
, all sectors are locked.
IL
IH
LKO
, sectors 0 and 1 (bottom boot) or sectors 132 and 133
for command definitions).
± 0.2 V, the standby current will be greater.
on the WP# pin, the device disables program and erase
on the WP# pin, the device reverts to whether the two
, the device does not accept any write cycles. This pro-
IH
, output from the device is disabled. The outputs are
for the timing diagram.
Am29BDS640G
CC
is greater than V
RH
after RESET# returns to
CC4
Table 13, “Command
). If RESET# is held
READY
LKO
(not during
Figure 20,
. The sys-
17