AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 28

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

Command Definitions
26
Reading Array Data
Set Burst Mode Configuration Register Command Sequence
Writing specific address and data commands or sequences into the command
register initiates device operations.
defines the valid register command sequences. Note that writing incorrect ad-
dress and data values or writing them in the improper sequence may place the
device in an unknown state. A reset command is required to return the device to
normal operation.
Refer to the AC Characteristics section for timing diagrams.
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data with the same exception. See the
Commands” section on page 35
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
on page 31
See also
quirements for Synchronous (Burst) Read Operation”
information. The Asynchronous Read and Synchronous/Burst Read tables provide
the read parameters, and Figures 11, 13, and
The device uses a burst mode configuration register to set the various burst pa-
rameters: number of wait states, burst read mode, active clock edge, RDY
configuration, and synchronous mode active. The burst mode configuration reg-
ister must be set before the device will enter burst mode.
The burst mode configuration register is loaded with a three-cycle command se-
quence. The first two cycles are standard unlock sequences. On the third cycle,
the data should be C0h, address bits A11–A0 should be 555h, and address bits
A19–A12 set the code to be latched. The device will power up or after a hardware
reset with the default setting, which is in asynchronous mode. The register must
be set before the device can enter synchronous mode. The burst mode configu-
ration register can not be changed during device operations (program, erase, or
sector lock).
“Requirements for Asynchronous Read Operation (Non-Burst)”
section for more information.
section for more information.
Am29BDS640G
Table 13, “Command Definitions,” on page 37
P r e l i m i n a r y
18
“Erase Suspend/Erase Resume
show the timings.
“Reset Command” section
sections for more
and
“Re-
25903C1 October 1, 2003