HYS64D128320GU-5-B Infineon, HYS64D128320GU-5-B Datasheet - Page 34

• Manufacturer Part Number: HYS64D128320GU-5-B
• Description: 184-Pin Unbuffered Dual-In-Line Memory Modules
• Manufacturer: Infineon

Table 19
Byte
23
24
25
26
27
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
Data Sheet
Description
Min. Clock Cycle Time at
CAS Latency = 2
Access Time from Clock for
CL = 2
Minimum Clock Cycle Time
for CL = 1.5
Access Time from Clock at
CL = 1.5
Minimum Row Precharge
Time
Minimum Row Act. to Row
Act. Delay
Minimum RAS to CAS Delay
t
Minimum RAS Pulse Width
t
Module Bank Density (per
Bank)
Addr. and Command Setup
Time
Addr. and Command Hold
Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time
t
Min. Auto Refresh Cmd Cycle
Time
Maximum Clock Cycle Time
t
Max. DQS-DQ Skew
X-Factor tQHS
SPD Codes for PC2100 Modules “–7F” (cont’d)
RCD
RAS
RC
CK
t
FRC
t
RRD
t
DQSQ
7.5 ns
0.75 ns
not supported
not supported
15 ns
15 ns
15 ns
45 ns
128 MByte/256 MByte
0.9 ns
0.9 ns
0.5 ns
0.5 ns
–
60 ns
75 ns
12 ns
0.5 ns
0.75 ns
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
36
Unbuffered DDR SDRAM Modules
256MB
1 rank
HEX
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
72
512MB
1 rank
HEX
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
72
SPD Contents
V1.1, 2003-07