HYS64D128320GU-5-B Infineon, HYS64D128320GU-5-B Datasheet - Page 24

• Manufacturer Part Number: HYS64D128320GU-5-B
• Description: 184-Pin Unbuffered Dual-In-Line Memory Modules
• Manufacturer: Infineon

7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
13) For each of the terms, if not already an integer, round to the next highest integer.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each
input)
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
Write command to 1
transition
DQS-DQ skew (DQS and associated DQ
signals)
Data hold skew factor
DQ/DQS output hold time
DQS input low (high) pulse width (write
cycle)
Data Sheet
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
measured between
t
cycle time.
HZ
RPRES
and
is defined for CL = 1.5 operation only
t
LZ
AC Timing - Absolute Specifications –6/–5
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
st
V
DQS latching
OH(ac)
and
V
OL(ac)
.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
DQSCK
CH
CL
HP
CK
DH
DS
IPW
DIPW
HZ
LZ
DQSS
DQSQ
QHS
QH
DQSL,H
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Min.
–0.7
–0.6
0.45
0.45
6
6
7.5
0.45
0.45
2.2
1.75
–0.7
–0.7
0.75
—
—
—
—
t
t
0.35
26
HP
QHS
min. (
DDR333
–
–6
t
CL
Max.
+0.7
+0.6
0.55
0.55
12
12
12
—
—
—
—
+0.7
+0.7
1.25
+0.40
+0.45
+0.50
+0.55
—
—
,
t
CH
)
Unbuffered DDR SDRAM Modules
Min.
–0.6
–0.5
0.45
0.45
5
6
7.5
0.4
0.4
tbd
tbd
–0.6
–0.6
0.75
—
—
—
—
t
t
0.35
HP
QHS
min. (
DDR400B
–
–5
t
t
CL
CK
Max.
+0.6
+0.5
0.55
0.55
12
12
12
—
—
—
—
+0.6
+0.6
1.25
+0.40
+0.40
+0.50
+0.50
—
—
,
is equal to the actual system clock
t
CH
) ns
t
DQSS
Electrical Characteristics
Unit Note/
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ns
ns
ns
ns
t
CK
CK
CK
CK
.
Test Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0
CL = 2.5
CL = 2.0
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
TFBGA
TSOPII
TFBGA
TSOPII
2)3)4)5)
2)3)4)5)
V1.1, 2003-07
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
1)