HYS64D128320GU-5-B Infineon, HYS64D128320GU-5-B Datasheet - Page 31
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HYS64D128320GU-5-B
Manufacturer Part Number
HYS64D128320GU-5-B
Description
184-Pin Unbuffered Dual-In-Line Memory Modules
Manufacturer
Infineon
Datasheet
1.HYS64D128320GU-5-B.pdf
(48 pages)
- Current page: 31 of 48
- Download datasheet (2Mb)
Table 18
Byte
18
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32
33
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35
Data Sheet
Description
Supported CAS
Latencies
CS Latencies
WE Latencies
SDRAM DIMM
Module Attributes
SDRAM Device
Attributes: General
Min. Clock Cycle Time
at CAS Latency = 2
Access Time from
Clock for
CL = 2
Minimum Clock Cycle
Time for CL = 1.5
Access Time from
Clock at
CL = 1.5
Minimum Row
Precharge Time
Minimum Row Act. to
Row Act. Delay
Minimum RAS to CAS
Delay
Minimum RAS Pulse
Width
Module Bank Density
(per Bank)
Addr. and Command
Setup Time
Addr. and Command
Hold Time
Data Input Setup Time 0.5 ns
Data Input Hold Time 0.5 ns
SPD Codes for PC2100 Modules “–7” (cont’d)
t
t
RCD
RAS
t
RRD
CAS latency = 2 & 2.5 0C
CS latency = 0
Write latency = 1
unbuffered
7.5 ns
0.75 ns
not supported
not supported
20 ns
15 ns
20 ns
45 ns
128 MByte/256 MByte 20
0.9 ns
0.9 ns
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
33
128MB
1 rank
HEX
01
02
20
C0
75
75
00
00
50
3C
50
2D
90
90
50
50
64
Unbuffered DDR SDRAM Modules
256MB
1 rank
HEX
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
64
256MB
1 rank
HEX
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
72
512MB
2 ranks
HEX
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
64
SPD Contents
V1.1, 2003-07
512MB
2 ranks
HEX
0C
01
02
20
C0
75
75
00
00
50
3C
50
2D
40
90
90
50
50
72
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