MC9328MXL ETC, MC9328MXL Datasheet - Page 78

• Manufacturer Part Number: MC9328MXL
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
In most of case, duty cycle is 50 / 50, therefore:
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
78
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
VSYNC
DATA[7:0]
PIXCLK
Ref No.
1
2
3
4
5
6
Figure 62. Sensor Output Data on Pixel Clock Rising Edge
csi_vsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
Table 32. Non-Gated Clock Mode Parameters
CSI Latches Data on Pixel Clock Falling Edge
1
MC9328MXL Advance Information, Rev. 5
Parameter
2
Valid Data
3
10.42
10.42
Min
180
1
1
0
Valid Data
5
Max
48
6
–
–
–
–
–
4
Valid Data
Unit
MHz
ns
ns
ns
ns
ns
Freescale Semiconductor