MC9328MXL ETC, MC9328MXL Datasheet - Page 57

no-image

MC9328MXL

Manufacturer Part Number
MC9328MXL
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9328MXLCVH
Manufacturer:
FREESCALE
Quantity:
12 388
Part Number:
MC9328MXLCVM15
Manufacturer:
Exar
Quantity:
136
Part Number:
MC9328MXLCVM15
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MXLCVM15R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MXLCVP15
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MXLCVP15R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MXLDVM15
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MXLDVM20
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9328MXLDVM20
Quantity:
600
Part Number:
MC9328MXLVF15
Manufacturer:
CRYSTRL
Quantity:
2
Part Number:
MC9328MXLVH20
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC9328MXLVM15
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Freescale Semiconductor
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.
3.13 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
DAT[1]
DAT[1]
For 4-bit
For 1-bit
DAT[2]
DAT[1]
CMD
For 4-bit
For 4-bit
CMD
S T
S
S
Interrupt Period
Block Data
Block Data
Content
******
CRC
E Z Z
E
Z Z L H
Figure 45. SDIO ReadWait Timing Diagram
E Z Z P
L L L L L L L L L L L L L L L L L L L L L H Z S
Figure 44. SDIO IRQ Timing Diagram
MC9328MXL Advance Information, Rev. 5
P S T
S
S
Response
CMD52
Block Data
CRC
Interrupt Period
E Z Z
L H
E Z Z
E
Z
Z
IRQ
S
Block Data
Block Data
******
******
S
Block Data
E
E
E
Z
Z Z
Specifications
IRQ
57

Related parts for MC9328MXL