MC9328MXL ETC, MC9328MXL Datasheet - Page 21

• Manufacturer Part Number: MC9328MXL
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Freescale Semiconductor
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 13.
Note:
Ref
No.
1
2
3
4
5
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
INT_DTACK
EXT_DTACK
CS5 asserted to OE asserted
External DTACK input setup from CS5
asserted
CS5 pulse width
External DTACK input hold after CS5 is
negated
OE negated after CS5 is negated
CS5
RW
HCLK
OE
1
2
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0
Characteristic
Table 13. Access Cycle Timing Parameters
MC9328MXL Advance Information, Rev. 5
3
5
4
Min
3T
–
0
0
0
1.8V ± 0.10V
Max
1.5T
4.5
T
–
–
Min
3T
–
0
0
0
3.0V ± 0.30V
Max
1.5T
T
–
–
4
Specifications
Unit
ns
ns
ns
ns
ns
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