COP8SG National Semiconductor, COP8SG Datasheet - Page 50

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

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14.0 Instruction Set
LD
LD
LD
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A, [B
A, [X
[B
A
A
A
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr.
±
],Imm
±
±
]
]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
CLeaR A
INCrement A
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
(Continued)
50
A [B], (B B
A [X], (X X
[B] Imm, (B B
A 0
A A + 1
A A − 1
A ROM (PU,A)
A BCD correction of A (follows ADC, SUBC)
C A7 … A0 C
C A7 … A0 C, HC A0
A7…A4
C 1, HC 1
C 0, HC 0
IF C is true, do next instruction
If C is not true, do next instruction
SP SP + 1, A [SP]
[SP] A, SP SP − 1
PU [VU], PL [VL]
PC ii (ii = 15 bits, 0 to 32k)
PC9…0 i (i = 12 bits)
PC PC + r (r is −31 to +32, except 1)
[SP] PL, [SP−1] PU,SP−2, PC ii
[SP] PL, [SP−1] PU,SP−2, PC9…0 i
PL ROM (PU,A)
SP + 2, PL [SP], PU [SP−1]
SP + 2, PL [SP],PU [SP−1],
skip next instruction
SP + 2, PL
[SP] PL, [SP−1] PU, SP−2, PC 0FF
PC PC + 1
A3…A0
±
[SP],PU [SP−1],GIE 1
±
1)
1)
±
1)