COP8SG National Semiconductor, COP8SG Datasheet - Page 20

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

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5.0 Functional Description
5.11 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
Bit 7
Bit 7
Reserved
Bit 7
T1C3
HC
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA
EXPND
BUSY
EXEN
GIE
Reserved This bit is reserved and must be zero
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
C
T1C2
LPEN T0PND
T1PNDA
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T1C1
T1ENA
T0EN µWPND
T1C0
EXPND
MSEL
µWEN
BUSY
IEDG
T1PNDB
(Continued)
EXEN
SL1
T1ENB
Bit 0
Bit 0
GIE
SL0
Bit 0
20
T2CNTRL Register (Address X'00C6)
The T2CNTRL control register contains the following bits:
T3CNTRL Register (Address X'00B6)
The T3CNTRL control register contains the following bits:
6.0 Timers
Each device contains a very versatile set of timers (T0, T1,
T2 and T3). Timer T1, T2 and T3 and associated autoreload/
capture registers power up containing random data.
6.1 TIMER T0 (IDLE TIMER)
Each device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0. The Timer
T0 runs continuously at the fixed rate of the instruction cycle
clock, t
which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
T2C3
Bit 7
T3C3
Bit 7
T1ENB
T2C3
T2C2
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB
T2ENB
T3C3
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
C
T2C2
T3C2
. The user cannot read or write to the IDLE Timer T0,
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 mode control bit
Timer
modes 1 and 2, T3 Underflow Interrupt Pend-
ing Flag in timer mode 3
Timer T3 Interrupt Pending Flag (Autoreload
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
Timer T3 Interrupt Pending Flag for T3B cap-
ture edge
Timer T3 Interrupt Enable for Timer Underflow
or T3B Input capture edge
T2C1
T3C1
T2C0
T3C0
T2
T3
T2PNDA
T3PNDA
Start/Stop
Start/Stop
T2ENA
T3ENA
control
control
T2PNDB
T3PNDB
in
in
T2ENB
T3ENB
timer
timer
Bit 0
Bit 0