COP8SG National Semiconductor, COP8SG Datasheet - Page 22

• Manufacturer Part Number: COP8SG
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory/ Two Comparators and USART
• Manufacturer: National Semiconductor

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6.0 Timers
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB con-
trol flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.
Figure 17 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
6.2.3 Mode 3. Input Capture Mode
Each device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the in-
put capture mode. In this mode, the reload registers serve as
independent capture registers, capturing the contents of the
timer when an external event occurs (transition on the timer
input pin). The capture registers can be read while maintain-
ing count, a feature that lets the user measure elapsed time
and time between events. By saving the timer value when
FIGURE 17. Timer in External Event Counter Mode
used as the counter input clock.
(Continued)
FIGURE 18. Timer in Input Capture Mode
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the external event occurs, the time of the external event is
recorded. Most microcontrollers have a latency time be-
cause they cannot determine the timer value when the exter-
nal event occurs. The capture register eliminates the latency
time, thereby allowing the applications program to retrieve
the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed t
rate. The two registers, RxA and RxB, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag Tx-
ENA allows the interrupt on TxA to be either enabled or dis-
abled. Setting the TxENA flag enables interrupts to be gener-
ated when the selected trigger condition occurs on the TxA
pin. Similarly, the flag TxENB controls the interrupts from the
TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 18 shows a block diagram of the timer T1 in Input
Capture mode. Timer T2 and T3 are identical to T1.
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